So-called surface technologies (in contrast with bulk technologies) enable the size of electromechanical structures (MEMS and/or NEMS) made on silicon to be reduced. These technologies rely on using a stack of at least three layers: a mechanical layer (typically 0.1 micrometer (μm) to 100 μm thick); a sacrificial layer (typically 0.1 μm to a few μm thick); and a support (typically 10 μm to 1000 μm thick). Selective chemical etching of the sacrificial layer makes it possible to provide functional structures in the mechanical layer that are locally independent of the support.
The non-etched zones of the sacrificial layer enable so-called “anchor” zones or mechanical reinforcement zones (or “pillars”) to be made that serve to connect the mechanical structure to the support.
In known methods that enable such pillars to be incorporated, e.g. the method described in application WO 2006/035031, a silicon substrate is assembled by molecular bonding to the top of the oxide layer, which oxide layer then acts as the sacrificial layer during final fabrication of the MEMS. During the final fabrication, trenches are formed through the silicon substrate that has been assembled by molecular bonding and the sacrificial layer is removed. The pillars serve to support the microsystem. During that operation, the interface zone between the added substrate and the remainder of the structure is subjected to chemical etching (in general with HF acid), thereby leading to shapes that are poorly controlled if the interface is not perfect, since the speed of etching is variable, and there is a risk of revealing the bonding interface. After the sacrificial layer has been removed, and the MEMS structure has been released, mechanical integrity is not good.
Other known methods that reflect that drawback are described in particular in U.S. Pat. No. 6,916,728 (FIGS. 9 and 10; column 6, lines 20 to 47) and U.S. Pat. No. 6,952,041 (FIGS. 4a to 4f; column 8; line 28 to column 9, line 49).
The article by T. Yamamoto et al. “Capacitive accelerometer with high aspect ratio single crystalline silicon microstructure using the SOI structure with polysilicon-based interconnect technique”, published in MEMS 2000, the thirteenth annual international conference, Jan. 23-27, 2000, Miyazaki, Japan, pp. 514-519 does not present that drawback. Nevertheless, the pillars are made of thick poly-Si and their lateral size is limited by the technology. The pillars are made in the sacrificial layer by filling from a deposit of poly-Si. Filling takes place via the flanks of the cavity so the thickness of the filling is greater than half the width of the pillars. In order to avoid depositing layers of poly-Si that are too thick (typical maximum 3 μm), the lateral size of the pillar is typically limited to 5 μm.
If filling takes place via the bottom of the cavity, the thickness to be deposited is than about 3 times to 5 times the thickness of the sacrificial layer so as to enable the layer to be planarized.
The article by G. J. O'Brien and D. J. Monk entitled “MEMS process flow insensitive to timed etch induced anchor perimeter variation on SOI and bulk silicon wafer substrates”, published in IEEE 2000, pp. 481-484, and U.S. Pat. No. 6,913,941, in particular its FIGS. 27 and 28, show pillars that pass both through the sacrificial layer and through the mechanical layer. In that configuration also, the cavities are filled via the flanks thereby limiting the lateral size of a pillar. Filling with poly-Si may be preceded by depositing a fine nitride layer to insulate the outside of the pillar.
Known methods are therefore limited to pillars of width that is limited to the thickness of the poly-Si layer used for filling them. For reasons of technology and of expense, the thicknesses used are typically of the order of a few μm, thereby limiting the lateral dimensions of pillars to a few μm.
There is another reason why known methods limit the lateral dimensions of pillars that are filled using poly-Si when the method contains a step of bonding a second silicon substrate (above-mentioned article by T. Yamamoto).
In order to make it easier to bond a first silicon substrate containing a thick layer (typically a few μm thick) of a material that is other than silicon (with different stress or expansion coefficients) on a second substrate of silicon, a known method consists in making a second layer of the second material on the other face of the first substrate with the same thickness as the first layer in order to compensate for the deformations induced by the differences between the said material and silicon, and make it easier to put the two substrates into contact during bonding. Such a method is described by Yamamoto, the first substrate containing as its thick layer at least the sacrificial layer of SiO2. In the known methods of making pillars in the sacrificial layer, the material used for filling is thick poly-Si. Since the stress state of polycrystalline Si (at the time of deposition or during heating) is different from that of SiO2, limiting the lateral dimensions of the pillars serves to limit non-uniformities in the sacrificial layer.